AI infrastructure hits a "wall"! Marvell: Copper interconnects and memory bottlenecks become key to the next stage of computing power expansion

The AI computing power competition is shifting from a simple chip race to a system-level game that encompasses interconnects, memory, and networking.

At the recent Six Five Summit 2026, Marvell executives pointed out that as inference models drive a surge in memory demand and data center scale breaks through physical limits, copper connectivity is nearing its performance ceiling, making optical interconnect and memory expansion technologies the core variables in the next phase of compute growth. Will Chu, Executive Vice President of Marvell’s Custom Cloud Solutions Business, stated, “The market has long focused on the XPU itself, but has overlooked the ‘attachment layer’ around the XPU—including network, memory, storage, and security.” “Behind every XPU, there are three to four, or even more, customization opportunities,” he said. “AI infrastructure is heading towards comprehensive customization.”

Dave Lazovsky, Executive Vice President of Data Center Networking Business Group, noted that the rise of inference time compute has caused KV cache demand to grow roughly tenfold in the past nine months. Memory capacity is no longer sufficient within a single rack, and scaling deployments require breaking into larger interconnect domains.

These judgments have direct investment implications for the market: memory manufacturers, optical interconnect suppliers, and custom silicon design companies are expected to keep benefiting from this structural demand. Analysts forecast that cumulative capital expenditures for global data center infrastructure from 2025 to 2030 will reach $4–5 trillion USD.

Dave Lazovsky characterizes the switch “from copper to optical” as a “forced function” for AI infrastructure, not an optional upgrade. The driver is the logic of model development itself: the first-generation hyperscale foundation models established the basic requirement for total memory capacity, while the emergence of inference models—on top of explosive KV cache growth—means that the HBM capacity inside a single rack can no longer support state-of-the-art models.

“You have no choice,” he said. “You must scale the interconnect domain from 144 XPUs to the next wave of about 576 XPUs in a pod, and continue scaling upward.” The physical premise for this expansion is the transition from copper-based interconnect to optical interconnect.

Marvell is currently advancing both onboard optics (NPO) and co-packaged optics (CPO), and has implemented CPO solutions on switches using both Ethernet and UAL protocols. Will Chu added that Marvell can offer customers a complete migration path from traditional copper solutions to NPO and then on to CPO, and can extend customization across the full link—from compute unit to IO interface to switch port.

Dave Lazovsky particularly emphasized Marvell’s differentiated value in analog SerDes technology: compared to traditional 2.4T SerDes optical links, a network scaled up based on analog SerDes can reduce power consumption by about fourfold, and after full deployment could cut overall data center power consumption by more than 25%. Amid severe shortages in power infrastructure, this efficiency advantage is rapidly gaining strategic importance.

Will Chu described the memory bottleneck as the core engineering challenge facing AI infrastructure and broke down Marvell’s strategic response into multiple levels from inside the chip to outside the rack.

Inside the chip, Marvell is investing in proprietary high-density SRAM IP, using tightly coupled design with compute units to boost performance and support the residency of larger models on the chip. He noted that traditional general-purpose memory compilers can no longer meet customer requirements.

Externally, the path is as follows: integrating customized HBM for greater bandwidth and capacity; employing 3D stacking technology to place memory directly atop logic chips; utilizing CXL or proprietary protocols for memory expansion—trading capacity for bandwidth; and introducing Photonic Fabric Memory devices, launched by Marvell at FMS, which provide up to 32TB of external memory pool within a standalone rack space.

Dave Lazovsky further explained that the Photonic Fabric Memory system combines the capacity and cost benefits of DDR with the high bandwidth and parallelism of HBM’s multiple pseudo channels. The goal is to let customers independently scale memory capacity and bandwidth for the first time, entirely decoupled from compute resources.

Will Chu added that surging memory prices are forcing hyperscale cloud operators to re-examine their entire infrastructure architectures. Demand for Marvell’s CXL products has grown significantly, partly from customers wanting to connect old memory to new servers and achieve twice the effective capacity through memory compression. Flash-level memory tiering solutions have also entered vendors’ consideration as a more cost-effective capacity supplement.

Dave Lazovsky pointed out that about four companies occupy over 75% of the total addressable market for data center infrastructure. This highly concentrated market structure allows Marvell to implement a business model very different from serving a broadly distributed customer base—embedding itself deep within customers’ development teams to jointly architect next-generation switch requirements years in advance.

He described three major current paths for scaling networks: some vendors prefer Ethernet solutions; a second route adopts the UAL protocol—essentially a high-performance network, similar to NVLink, that uses memory-semantic load/store operations, which Dave Lazovsky believes is more efficient than Ethernet packet transport; one other vendor is rolling out a wholly self-developed proprietary network topology.

Will Chu added that the tight coupling between XPUs and scale-up networks inevitably leads to deep customization at the protocol and optimization levels, eventually manifesting in custom silicon. “Not every company can deliver end-to-end,” he said. “But we can do so, and act as an extension of the customer’s development team, directly participating in the design of their core infrastructure.”

Dave Lazovsky also remarked that Marvell’s longstanding trusting relationships with top hyperscalers and GPU makers are among the company’s most important assets: “It takes years to build, and we have that trust already.”

The following is the full interview transcript:

Patrick Moorhead｜00:17

Welcome to Six Five Summit 2026. This year’s theme is “Unleashing AI Potential.” Co-hosting with me is Daniel Newman. How have you been, my friend?

Daniel Newman｜00:38

Pretty good. The changes this year are truly amazing: Compute power is of course still very important, but connectivity has taken center stage, and there’s so much discussion around it.

We’ve always moved from one bottleneck to the next. As you said, connectivity is the focus now, but this year we’ve faced almost every conceivable bottleneck. It started with compute, then the CPU overtook the GPU in importance, then memory became key. Later, the focus shifted from mere connectivity to optical interconnect. And if you want, we could talk about power as well. Pat, it’s one hot topic after another—it really is a remarkable year.

Patrick Moorhead｜01:02

We’re at Marvell headquarters now, and coming up we’ll discuss custom chips, memory, and interconnect. Let me introduce Will and Dave—so glad to have you both.

Dave Lazovsky｜01:14

Thank you so much for inviting us.

Patrick Moorhead｜01:16

I’m really looking forward to this conversation. I’ve seen you both speak onstage, and I’ve attended your analyst days and product briefings. It’s great to have you at Six Five today.

Daniel Newman｜01:26

Glad you’re both here, and congratulations—you’ve just completed an acquisition, which sounds like it’s off to a great start. Of course, there’s still a lot of work ahead.

Pat, you mentioned connectivity. What’s interesting about Marvell is that you’re involved in nearly all aspects: chips, memory, connectivity, as well as scale-up, scale-out, and scale-across. You have a presence in every field, doing whatever needs to be done.

Daniel Newman｜01:49

Do you think people know the movie “Mr. Mom”? I think they do. Let’s see.

Will, let me start with you. The business you lead is one of the fastest growing in the semiconductor sector. I recall Jensen Huang once called you the next trillion-dollar company—that’s a bit of pressure, but you’re certainly heading in that direction.

Daniel Newman｜02:12

It’s fair to say that Marvell’s emergence over the last few years has largely been thanks to the custom silicon business. But you’re also involved in memory expansion architectures, scale-up networks, and scale-across interconnects—a very broad set.

I’d love to hear your overall perspective. The market is highly focused on XPUs and custom silicon—where is that focus appropriate, and what’s getting missed? As we mentioned, this AI boom is being driven by many factors, not just the XPU itself.

Will Chu｜02:52

Great question, Daniel.

Daniel Newman｜02:54

Took a bit of buildup to get to it.

Will Chu｜02:55

And thank you both for coming to Marvell. The market really does see the XPU as the main component of AI infrastructure needing customization, so we spend a lot of time talking about what we call “XPU Attach”—the complementary components around the XPU.

At a high level, we’re seeing that all aspects of AI infrastructure are moving toward customization. The XPU itself of course has to be tailored to the workload, but the surrounding layers—network, memory, storage, and even security—must be customized too. We’re involved in all these technical categories, supporting the XPU and boosting infrastructure performance.

There are a lot of opportunities. For each XPU, you might see three, four, or even more XPU Attach opportunities supporting next-gen products. These are combined with our connectivity and networking solutions. So we genuinely provide comprehensive end-to-end solutions.

Daniel Newman｜04:06

I think if the market only understands you as an XPU company, they’re missing a big piece of the story.

Dave Lazovsky｜04:10

Absolutely. One of the major opportunities is Will’s team’s work on custom XPUs, which includes input/output, or I/O. Marvell is one of the leaders in I/O technology.

Right now, both the media and the market are giving a lot of attention to optical interconnect. I believe we have the strongest team in the world in this area. Complementary to that is our SerDes—serializer/deserializer—technology: it’s at 224 Gbps and moving quickly to 448 Gbps. Integrating these technologies at the XPU endpoint lets us optimize the entire network solution, including scale-up interconnects.

Dave Lazovsky｜04:55

The interesting thing about the current market is not just its size—the largest infrastructure build-out in human history—but also its concentration. Four companies account for over 75% of the total serviceable market for data center infrastructure.

This lets us use a business model totally different from serving forty separate companies. We can truly deliver to these customers’ needs, customizing not just the XPU but also the scale-out and scale-up networks.

It’s a unique chance for us to work closely with customers who, in practice, view us as an extension of their development teams.

Daniel Newman｜05:43

Fascinating. We just released a new forecast estimating cumulative capital spend to 2030—guess what the number is now?

Dave Lazovsky｜05:57

I was going to say $4.5 trillion.

Daniel Newman｜05:59

Four to five trillion, yes. But total data center infrastructure investment stands at $12 trillion. You’re probably only thinking about chips; we’re considering the entire infrastructure. If it’s just chips, your estimate is about right.

By the way, less than a quarter ago our forecast was $10.7 trillion. That shows how big and fast-moving this opportunity is—almost hard to keep up.

Patrick Moorhead｜06:19

I mentioned earlier that balance between different parts of the network and system has always been important—it’s just a question of what part is the weakest link.

In basic system architecture, whether GPU or XPU, when a single tray can’t meet demand, you expand to the whole rack. If one rack isn’t enough, you connect to others. When you integrate a lot of clusters, you might even need to connect to another data center to get the job done.

Patrick Moorhead｜06:52

There’s a debate now—not just on X but also on earnings calls—about when co-packaged optics, or CPO, will see true mainstream adoption. We won’t argue about CPO form factors—but is the XPU going to be the key force driving CPO into the mainstream?

Dave Lazovsky｜07:16

I think, fundamentally, the driving force comes from AI infrastructure. If you ask what makes scale-up networks switch from copper to optical an imperative rather than a nice-to-have, the answer lies in the models.

The earliest massive foundation models with trillions of parameters drove up total memory demands for a scale-up domain. In the past 24 months, the change has come from inference models—performing more computation at inference time. This adds to the base parameter storage with an even greater need for KV cache. The size of the KV cache has grown tenfold in just the past nine months, and all of that needs memory. That’s why memory companies like Micron and SK Hynix now have trillion-dollar market caps.

The only way to provide the necessary service model capacity in high-bandwidth memory, HBM, is to scale outside the rack. There’s no other option. You have to go beyond 144 interconnected XPUs; next, pods of about 576 XPUs, and then beyond that.

Patrick Moorhead｜08:35

In this transition, where does Marvell sit? Let’s narrow it to CPO for scale-up networks.

Dave Lazovsky｜08:45

We’re implementing co-packaged optics in several ways. Right now, there’s interest in the difference between near-packaged optics (NPO) and CPO—meaning onboard or NPO versus CPO. For us, whichever way the customer asks, the answer is “yes”—the form factor doesn’t really matter, since we have a full suite of optical interconnect solutions.

With our own switch silicon, we’re confident we can deploy CPO directly on the package. Now, we do this on Ethernet-based systems and those using UALink for scale-up as well.

We also have solutions at the XPU endpoint. There are both ongoing CPO and NPO customer projects. Having NPO for first-wave optical deployments helps customers adopt the technology more confidently. Of course, each approach has its trade-offs.

Will Chu｜09:47

To add to Dave’s point about the XPU endpoint: Traditionally, you might develop a copper-based solution like an IO chiplet, but when you approach the limit of copper and need to transition to optics, the portfolio we’ve already shown on the switch side can also be used at the XPU endpoint. We can help customers move from copper to NPO, and then to CPO.

According to customers’ transformation speed, pace, and requirements, we can customize the full solution: from compute to IO, extending to the other end’s switch, both directions. We have a complete product portfolio and technical solutions.

Dave Lazovsky｜10:24

One last thing: The value of having the same IOs at both ends of the link is critical—especially for scale-up links. You need rock-solid links in a scale-up network.

Whether it's 224 Gbps copper SerDes on both ends of an XPU-to-scale-up switch link, or both ends equipped with our optics, it’s the same principle.

Our optics portfolio includes the so-called Fast Pipe, evolving from 200 Gbps to 400 Gbps, and what was called the “Flat Pipe”—with 56 Gbps nonreturn-to-zero (NRZ) moving toward around 112 Gbps. Analog SerDes is vastly more power-efficient.

Will Chu｜11:05

Another detail: Very few companies can do true end-to-end solutions—we’re one of them. We literally sit down with customers to design both ends of the link and figure out how next-generation infrastructure will meet their needs. That brings us back to the original theme: We are not just an XPU company.

Daniel Newman｜11:25

Indeed, the focus used to be almost entirely on the XPU.

Patrick Moorhead｜11:27

That was a wild period, but after a few market cycles, people are starting to understand the whole picture.

Daniel Newman｜11:35

We’ve interviewed your President & COO Chris Koopmans several times on Six Five—he’s had great things to say about this topic. People should check those out.

You just mentioned the “memory wall.” The timing is fascinating—memory used to be a homogeneous commodity, with negative double-digit margins; now it’s seeing some of the best profits in the industry.

Daniel Newman｜12:02

Credit where it’s due—especially for companies not just making NAND and DRAM but also advancing HBM, which made these gains possible.

You’ve used a variety of approaches here: high-density SRAM, memory pooling, and many creative architectures. I believe every chip company today is trying to break the memory wall. Even if you get around one bottleneck, you’ll still need more RAM, so the future looks good for memory vendors—I think we all agree on that.

Can you talk about the different technologies you’re using, and the trade-offs? The market would love to know how Marvell is thinking about this.

Will Chu｜12:41

Daniel, I’ll take this one. As Dave mentioned, the bigger the model, the more memory you need—it’s a direct ratio. Meanwhile, prices are rising, and traditional approaches are becoming bottlenecks across the system.

Will Chu｜13:00

Within Marvell and with our customers, we’re looking at multiple ways to breach the memory wall.

First, high-density static random access memory, or SRAM. This involves using specialized IP inside the chip to push memory density way up, tightly coupling it with compute units for better performance and the ability to host larger models on-chip.

This is a custom solution. Relying on standard memory compilers just won’t cut it anymore, so we’re pouring a lot of resources here. That’s inside the chip.

Will Chu｜13:35

Next, on or above the chip. That means HBM, of course. And wherever possible, we push for custom HBM to boost both bandwidth and capacity.

Another technology is 3D stacking—putting memory atop the die for closer memory-logic coupling.

Then, expansion further out. This includes traditional memory expansion via CXL or proprietary methods, directly adding physical memory. This may compromise on bandwidth, but you’re no longer limited by physical space so you gain lots more capacity. Beyond that, there are options for external, disaggregated memory outside the tray.

Will Chu｜14:26

Let me give an example for Dave: We announced the Photonic Fabric memory device at FMS. It provides 32TB of memory in a standalone rack, completely separate from the compute device. So it truly is end-to-end.

And, “near-memory compute”: You place compute close to memory, offloading certain CPU or GPU workloads onto compute units fused with large memory for higher overall utilization.

That’s all happening now. Back to Dave’s earlier point—increasing capacity and scaling memory drives demand for more I/O and connectivity, because you still need to move data throughout the infrastructure.

Daniel Newman｜15:19

They’re interdependent and collaborative. There’s a debate trending on social media: “Is the memory boom over and the era of optics here?” But as you said, it’s not an either/or—you need both.

Will Chu｜15:35

I’d say they drive each other forward.

Patrick Moorhead｜15:36

If they all do their job well, compute, memory, and storage continuously push one another ahead in cycles of evolution.

By the way—I’ve never seen such intense focus on CXL. One of our analysts wrote a white paper on it three or four years ago—specs were just coming out, lots of buzz, but pooling hadn’t landed yet. Now demand is immense, and you’ve been investing four or five years, maybe longer. It seems poised for a real breakthrough moment.

Dave Lazovsky｜16:07

It’s starting to deploy, and much of it is still driven by inference models and compute at inference. People need low latency, rapid access to huge, high-bandwidth RAM.

As Will mentioned, with the Photonic Fabric memory device, we try to spare customers from having to choose: On one hand, there’s DDR’s capacity and cost structure—we integrate DDR into our system. On the other, HBM’s bandwidth and multi-pseudo channel parallelism—this gives huge throughput and supports parallel memory transactions for latency hiding.

So you get the best of both. The system should let our customers, and their customers, scale memory capacity and bandwidth independently of compute resources for the first time.

Patrick Moorhead｜17:04

Fascinating. Who would’ve thought five or six years ago, when the first specs hit, that we’d be here with LLMs, agents, and all that followed?

Will Chu｜17:14

One more point: Sky-high memory prices are indeed forcing hyperscale cloud architects to rethink their entire infrastructure—especially as high prices look set to persist.

There's strong demand for our CXL products. Some customers want to recycle old memory and plug it into new servers, but older memory can’t connect directly to new servers, CPUs, or GPUs. We can bridge that gap.

We support memory compression and deep compression, letting customers squeeze double the effective capacity out of a fixed amount of RAM chips. As we discussed, pooling is advancing to maximize utilization.

Finally, we’re seeing extended demand for flash—a further outer tier. Whether it’s high-bandwidth flash (HBF) or traditional flash for certain use cases, there’s massive demand. Back to Dave’s point: customers are now experimenting with usable memory tiering, leveraging flash’s lower cost compared to DRAM to gain more capacity. All this further drives connectivity demand.

Daniel Newman｜18:21

It’s proof that necessity is the mother of invention. All this is driven by the need to improve margins. The same applies to suppliers—every time you roll out something that improves compute, people will use more of it.

Daniel Newman｜18:37

The scale's not small. In one Six Five Summit session with Google, they said they process 40 trillion tokens per month. Google alone—40 trillion tokens.

Will Chu｜18:49

That’s just incredible.

Patrick Moorhead｜18:51

On network customization: This industry always seems to cycle like an accordion—first it’s about scale and templates, standardized everything, then a bottleneck appears and you realize customization is a must.

Every hyperscale cloud has its current architecture, must manage it and try to evolve it. So, why does the scale-up network need customization? The reasons might be obvious, but you’ve mentioned the value of end-to-end solutions, meaning one vendor across the whole chain. Dave, your thoughts?

Dave Lazovsky｜19:37

It comes back to this concentrated market: major hyperscalers dominate, and no two use the exact same standardized AI infrastructure. Especially with scale-up networks, they’re developing their own custom solutions—at both the physical and logical layers.

You see some convergence—it’s not quite standardization, but at both layers, there’s alignment. Two, maybe four are leaning toward Ethernet-based scale-up. Others favor the UALink path—a higher-performance, NVLink-like scale-up network using memory-semantic load/store, essentially more efficient than packet-moving over Ethernet.

Another player uses a fully custom, proprietary network topology.

Dave Lazovsky｜20:41

Whatever the approach, what we build for customers is always highly customized: from XPU companion chips to IO chiplets, often even down to bespoke protocol layers, to match requirements.

We look at channel specs, tune FEC (forward error correction), to balance: excellent BER and link stability, power, and switching chip latency.

It’s the same with switches. This is not just the world of generic merchant chips anymore. We co-architect the switch with hyperscalers years ahead, so we deliver exactly what they’ll need when the time comes.

Will Chu｜21:29

I’d add, Dan, given $10+ trillion of capital at stake, there’s a strong economic case for optimizing your infrastructure.

Will Chu｜21:41

XPUs and their scale-up networks must be tightly coupled to reach performance goals. That inevitably means custom protocols and optimization measures, implemented in our chips.

Will Chu｜22:01

That’s the value we provide, and that’s our unique advantage.

Frankly, it’s not easy—it’s actually very hard. But we keep doubling down on engineering capacity, and with a track record and customer trust, we can carry that responsibility. After all, these are the most critical pieces of their infrastructure.

Daniel Newman｜22:22

Let me tie it together. The Six Five Summit 2026 theme is “Unleashing AI Potential,” and you’re enabling customers to unlock solutions through partnership.

To clarify for the audience, they rarely—if ever—disclose who the customers are. But these are the massive hyperscalers, some of the world’s biggest companies. Marvell builds fully custom solutions for them, full of stories worth knowing.

Daniel Newman｜22:46

Will, back to this: Within Marvell’s public, discussable work—I know you won’t disclose the biggest secrets online (we wouldn’t mind!), but among what’s public, what do you think will be most transformative, meeting AI’s seemingly infinite need for capacity and capability? You do so much at Marvell, it’s not easy to choose just one.

Will Chu｜23:15

This is a broad question—it’s hard to pick only one.

Daniel Newman｜23:19

List a few, then. I’ll ask Dave to add to yours.

Will Chu｜23:27

At the foundation, there are three elements. First, connectivity—Dave will speak to this, we do a lot in that space.

For memory, we’re making huge breakthroughs to deliver high-density, fully optimized memory. Cracking the memory wall is key.

Memory, of course, is intertwined with compute. Compute is better understood, and more quickly solved by engineering. But where demand dynamics change fundamentally is memory.

Paired with our IO technology—which Dave will discuss—we can combine all three. That capability is truly unique.

Dave Lazovsky｜24:15

We haven’t spent much time on scale-out (horizontal) and scale-across (cross-domain), but both are major growth areas for us. Data center campuses are only getting bigger.

Dave Lazovsky｜24:27

I remember Mark Zuckerberg saying Meta’s latest data center is about as large as Manhattan. Think of those interconnect needs—it’s mind-blowing. That’s driving demand for a new optical interconnect technology called “Coherent-lite,” designed for <10 km, and it’s growing fast.

Marvell’s coherent optics team is phenomenal—I’ve never seen anything like it. We brought 1.6 Tbps optical interconnect to market first—it’s astounding. Cross-domain scaling is hot, and so is scale-out.

But we believe one thing might prove truly transformative.

Dave Lazovsky｜25:17

Within the data center, about 85% of traffic is intra-scale-up—between scale-up processors, with 15% for scale-out.

If we improve efficiency here, especially energy, it’ll slash total data center power consumption. Power is already constrained and, in the next 3–5 years (at least in the US), insufficient for new data center builds.

So, what we’re doing—or in fact have developed and are deploying—is an analog SerDes-based optical scale-up network. Versus simply adding optics atop traditional 224 Gbps SerDes links, this reduces power to about a quarter.

We believe this will be huge: Once fully deployed, it could cut total data center power by over 25%.

Daniel Newman｜26:34

I was about to ask: By how much? We need hundreds of new gigawatts of power. Fuel cells are limited, so are other means; nuclear’s a wish for the future, and grid interconnects take seven years, gas turbines also take years to deliver.

So, every gigawatt you save means more output—a massive opportunity.

By the way, I know Terafab isn’t a data center. But speaking of Meta’s facilities, I think “Central Park” is the right size for comparison—they even overlay the outlines for reference.

Will Chu｜27:02

That’s correct.

Daniel Newman｜27:03

But these buildings are truly monumental—we can all agree. Any final thoughts?

Will Chu｜27:10

Adding on to Dave’s point, the real core advantage is that we have all this foundational technology and can integrate it.

Some companies may offer a few pieces of IP, but integrating it takes a full suite: memory, IO, and networking, with the ability to combine them or distribute them across different silicon—while ensuring they work together cohesively.

Will Chu｜27:39

Achieving true end-to-end cohesion is very challenging. Ultimately, our core strength is our complete and high-quality IP portfolio, plus the ability to make it all work at AI infrastructure scale. That’s what we keep delivering daily.

Daniel Newman｜27:55

Pursuing opportunities beyond the core silicon, capturing the attach surrounding it, is indeed a successful path.

Dave Lazovsky｜27:59

Beyond technology depth and breadth, and our world-class team, one other thing is often overlooked: the depth of our customer relationships.

Dave Lazovsky｜28:12

As someone relatively new to Marvell, I see it as one of the company’s most important assets. This kind of trust takes years to establish.

You could say we now have these relationships—years in the making—with the four major hyperscalers and GPU makers. Being able to work as an extension of the development teams at some of the world’s largest companies—it’s special.

Patrick Moorhead｜28:42

I’ve heard that from your customers—and I’m sure Daniel has, too—even if it’s hard for them to say publicly. I’ve even seen surprising press releases supporting what you’re doing. Congratulations; deeply engaging with your customers can yield incredible results.

Daniel Newman｜29:03

Will and Dave—thank you both for such a deep and insightful discussion. You’ve given Six Five Summit viewers a lot of value. Congrats again on your progress and acquisitions. We look forward to following and reporting on Marvell moving forward.

Dave Lazovsky｜29:20

Thank you so much for having us.

Daniel Newman｜29:22

And thanks, everyone, for joining the “Semiconductor Spotlight” at Six Five Summit 2026. Stay tuned, subscribe, and check out our other summit discussions. Thank you, and see you at the next one!